1. Field of the Invention
The present invention relates in general to a process for fabricating semiconductor static random access memory (SRAM) devices. In particular, the present invention relates to a process for fabricating SRAM devices having reduced semiconductor die area for reduced device size as well as increased device memory storage capacity. More particularly, the present invention relates to a process for fabricating SRAM devices having stacked transistors in memory cells that results in the reduction of the overall surface area requirement of the SRAM devices.
2. Technical Background
Conventional SRAM devices are built around MOS transistors that constitute the memory cells which in turn form the memory array of the entire SRAM device. The key to the reduction of device size as well as the increased device storage capacity is the reduction of the memory cells themselves that constitute the backbone of an SRAM device. FIG. 1 of the accompanying drawing of the present invention shows the schematic diagram of such a memory cell of the conventional SRAM device.
As is seen in FIG. 1, the typical memory cell of a conventional SRAM device comprises four MOS transistors and two resistors, they are, namely, the first, second, third and fourth MOS transistors T1, T2, T3 and T4, and the first and second resistors R1 and R2 respectively. The resistors R1 and R2 serve as load components in the memory cell of the SRAM device. Electrically, the first resistor R1 and the first MOS transistor T1 are connected in series across the first and the second voltages, namely the power V.sub.DD and the ground V.sub.ss potentials of the SRAM device. A similar arrangement is made as well for the second resistor R2 and the second transistor T2, as is observed in the drawing.
The gate of the first MOS transistor T1 is connected to the junction between the series connection of the second resistor R2 and the second MOS transistor T2. That junction is denoted as node B in the drawing. In a similar way, the gate of the second MOS transistor T2 is connected to the node A that is the junction between the first resistor R1 and the first MOS transistor T1.
The source/drain pair of the third MOS transistor T3 is connected between the A node and a first bit line BL of the very memory cell discussed herein. The gate of this third MOS transistor T3 is connected to the word line WL of this memory cell. In a similar arrangement, the fourth MOS transistor T4 has its source/drain pair connected between the B node and a second bit line BL of the memory cell, while its gate is also connected to the word line WL.
When the node A is supplied with a logically high voltage signal, via the third MOS transistor T3, as a result of memory cell access through the addressing of the bit BL and word line WL, the second MOS transistor T2 is placed in its conduction state, and the node B is consequently pulled to the ground potential (i.e., V.sub.ss) of the system. As a result of the pulling down of node B, the first MOS transistor T1 is also forced into its blocking state, ensuring that the potential at the node A is maintained at the logical high state, nearly that of the system V.sub.DD voltage. On the other hand, when the node A is supplied with a logically low voltage signal, the second MOS transistor T2 will be placed in its blocking state, and the node B is consequently maintained at the V.sub.DD potential. This triggers the first MOS transistor T1 to enter its conduction state, ensuring that the potential at node B be maintained at the logical low state, nearly that of the system V.sub.ss voltage. Based on the inherent electrical potential holding nature of this logic circuitry, the memory cell can be used to statically store bits of data in the device.
Reference is now directed to FIG. 2 of the drawing, in which is shown the top view of the memory cell layout in the conventional SRAM device of FIG. 1, as fabricated onto, for example, a P-type semiconductor substrate. The field oxide layer 10 defines an active region 12 over the surface of the P-type semiconductor substrate 1. Layers of polysilicon 142, 144 and 146 are individually formed at selected locations on the active region 12 defined by the field oxide layer 10. Among these polysilicon layers, layer 142 is utilized as the gate terminal for the first MOS transistor T1, layer 144 is utilized as the gate terminal for the second MOS transistor T2, while layer 146 is utilized as the gate terminal for both the third and fourth MOS transistors T3 and T4, and is utilized as the word line WL for the memory cell. N.sup.+ -type doped regions are formed on the active region 12 at their respective locations to form the respective drain and source regions for the MOS transistors T1, T2, T3 and T4, as is seen in the layout view of FIG. 2. These N.sup.+ -type doped regions 122 are tied to system ground V.sub.ss.
The polysilicon region 142 is electrically coupled to both the second MOS transistor T2 and the fourth MOS transistor T4 through buried contacts 162 and 164 respectively. The coupling forms the node B as is also indicated in the top view. The polysilicon layer 144, on the other hand, is coupled to both the first and third MOS transistors T1 and T3 via the buried contact 166 forming the A node also clearly indicated in the drawing. For the purpose of clarity in the description, the first and second resistors R1 and R2 that also constitute part of the memory cell as shown in the schematic diagram of FIG. 1 are not shown in the layout view, although it can be appreciated by persons skilled in this art that they may be located on top of the MOS transistors T1, T2, T3 and T4 in the form of polysilicon layers.
Further, the first and second bit lines BL and BL fabricated out of proper metal material are further formed over the surface of the first and second resistors R1 and R2. Contacts 182 and 84 may be used to couple the bit lines to the third and fourth MOS transistors T3 and T4 respectively.
Based on the above general description of the semiconductor structural configuration of the memory cell found in the conventional SRAM devices, it is obvious that the four MOS transistors that constitute the backbone of the memory cell occupy a great percentage of the surface area on the substrate for the memory cell. This is because they are substantially formed on the same level over the available surface area of the substrate. The total surface area consumed by these transistor devices thus is the primary factor that determines the size of the memory cell, which in turn determines the level of integration that is possible for the SRAM device.